1 of 7 general description the DS1100 series delay lines have five equally spaced taps providing delays from 4ns to 500ns. these devices are offered in surface - mount packages to save pc b area. low cost and superior reliability over hybrid technology is achieved by the combination of a 100% silicon delay line and industry - standard max and so packaging. the DS1100 5 - tap silicon delay line reproduces the input - logic state at the output after a fixed delay as specified by the extension of the part number after the d ash. the DS1100 is designed to reproduce both leading and trailing edges with equal precision. each tap can driv e up to 10 74ls loads. maxim can customize standard products to meet special needs. features ? all - silicon timing circuit ? five taps equally spaced ? 5v operation ? delays are stable and precise ? both leading - and trailing - edge accuracy ? improved replacement for ds1000 ? low - power cmos ? ttl/cmos - compatible ? vapor - phase, ir, and wave solderable ? custom delays available ? fast - turn prototypes ? del ays specified over both commercial and industrial temperature ranges pin assignment pin description tap 1 to tap 5 - tap output number v cc - +5v gnd - ground in - input DS1100 5 - tap economy timing element (delay line) 19- 5735; rev 3/11 1 2 3 4 8 7 6 5 v cc tap 1 tap 3 tap 5 in tap 2 tap 4 gnd DS1100z so (150 mil s ) DS1100u max ? max is a registered trademark of maxim integrated products, inc.
DS1100 2 of 7 absolute maximum ratings voltage range on any pin relative to ground ........................... - 0.5v to +6.0v short - circuit output current ...................................................... 50ma for 1s operating temperature range .................................................... - 40c to +85c storage temperature range ........................................................ - 55c to +125c lead temperature (soldering, 10s) .............................................. +300 c solderi ng temperature (reflow) lead(pb) - free ........................................................................... +260 c containing lead(pb) ................................................................. +240 c this is a stress rating only and functional operation of the device at these or any other conditi ons above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. dc electrical characteristics (v cc = 5.0v 5%, t a = - 40c to +85 c , unless otherwise no ted .) parameter sym bol condition s min typ max units notes supply voltage v cc 4.75 5.00 5.25 v 5 high - level input voltage v ih 2.2 v cc + 0.3 v 5 low - level input voltage v il - 0.3 0.8 v 5 input - leakage current i i 0.0v v i v cc - 1.0 1.0 a active current i cc v cc = max; freq = 1mhz 30 50 ma 6, 8 high - level output current i oh v cc = min; v oh = 4 - 1 ma low - level output current i ol v cc = min; v ol = 0.5 12 ma ac electrical characteristics (v cc = 5.0v 5%, t a = - 40c to +85c , unless otherwise noted .) par ameter sym bol condition s min typ max units notes input pulse width t wi 20% of tap 5 t plh ns 9 input - to - tap delay tolerance (delays 40ns) t plh, t phl +25c 5v - 2 table 1 +2 ns 1, 3, 4, 7 0c to +70c - 3 table 1 +3 ns 1, 2, 3, 4, 7 - 40c to +85 c - 4 table 1 +4 ns 1, 2, 3, 4, 7 input - to - tap delay tolerance (delays > 40ns) t plh, t phl +25c 5v - 5 table 1 +5 % 1, 3, 4, 7 0c to +70c - 8 table 1 +8 % 1, 2, 3, 4, 7 - 40c to +85c - 13 table 1 +13 % 1, 2, 3, 4, 7 power - up time t pu 200 s input period period 2(t wi ) ns 9 capacitance (t a = +25c , unless otherwise noted. ) parameter symbol conditions min typ max units notes input capacitance c in 5 10 pf
DS1100 3 of 7 notes: 1) initial tolerances are with respect to the nominal value at +25c and 5v for both leading and trailing edge. 2) temperature and voltage tolerance is with respect to the nominal delay value over the stated temperature range, and a supply - voltage range of 4.75v to 5.25v. 3) all tap d elays tend to vary unidirectionally with temperature or voltage changes. for example, if tap1 slows down, all other taps also slow down; tap3 can never be faster than tap2. 4) intermediate delay values are available on a custom basis. for further information, email the factory at custom.oscillators@maxim - ic.com . 5) all voltages are referenced to ground. 6) measured with outputs open. 7) see test conditions section at the end of this data sheet. 8) frequencies higher than 1mhz result in higher i cc values. 9) at or near maximum frequency the delay accuracy can vary and will be application sensitive (i.e., decoupling, layout). figure 1. logic diagram figure 2. timing diagram: silicon delay line
DS1100 4 of 7 terminology period: the time elapsed between the leading edge of the first pulse and the leading edge of the following pulse. t wi (pulse width): the elapsed time on the pulse between the 1.5v point on the leading edge and the 1.5v point on the trailing edge, or the 1.5v point on the trailing edge and the 1.5v point on the leading edge. t rise (input rise time): the elapsed time between the 20% and the 80% point on the leading edge of the input pulse. t fall (input fall time ): the elapsed time between the 80% and the 20% point on the trailing edge of the input pulse. t plh (time delay, rising): the elapsed time between the 1.5v point on the leading edge of the input pulse and the 1.5v point on the leading edge of any tap outp ut pulse. t phl (time delay, falling): the elapsed time between the 1.5v point on the trailing edge of the input pulse and the 1.5v point on the trailing edge of any tap output pulse. test setup description figure 3 illustrates the hardware configuration used for measuring the timing parameters on the DS1100. the input waveform is produced by a precision - pulse generator under software control. time delays are measured by a time interval counter (20ps resolution) connected between the input and each tap. ea ch tap is selected and connected to the counter by a vhf switch control unit. all measurements are fully automated, with each instrument controlled by a central computer over an ieee 488 bus. test conditions input ambient temperature: +25c 3c supply voltage (v cc ): 5.0v 0.1v input pulse: high = 3.0v 0.1v low = 0.0v 0.1v source impedance: 50 ? max rise and fall time: 3.0ns max (measured between 0.6v and 2.4v) pulse width: 500ns (1s for - 500 version) period: 1s (2s for - 500 version) output: e ach output is loaded with the equivalent of one 74f04 input gate. delay is measured at the 1.5v level on the rising and falling edge. n ote : above conditions are for test only and do not restrict the operation of the device under other data sheet condi tions.
DS1100 5 of 7 figure 3. test circuit table 1. DS1100 part number delay part DS1100 - xxx nominal delays (ns) tap 1 tap 2 tap 3 tap 4 tap 5 - 20 4 8 12 16 20 - 25 5 10 15 20 25 - 30 6 12 18 24 30 - 35 7 14 21 28 35 - 40 8 16 24 32 40 - 45 9 18 27 36 45 - 5 0 10 20 30 40 50 - 60 12 24 36 48 60 - 75 15 30 45 60 75 - 100 20 40 60 80 100 - 125 25 50 75 100 125 - 150 30 60 90 120 150 - 175 35 70 105 140 175 - 200 40 80 120 160 200 - 250 50 100 150 200 250 - 300 60 120 180 240 300 - 500 100 200 300 400 500
DS1100 6 of 7 orde ring information part temp range pin - package DS1100z - xxx - 40 c to +85 c 8 so DS1100z - xxx/t&r - 40 c to +85 c 8 so DS1100z - xxx + - 40 c to +85 c 8 so DS1100z - xxx +t - 40 c to +85 c 8 so DS1100u - xxx - 40 c to +85 c 8 max DS1100 u - xxx /t&r - 40 c to +85 c 8 max DS1100u - xxx+ - 40 c to +85 c 8 max DS1100u - xxx+ t - 40 c to +85 c 8 max xxx denotes total time delay (ns) (see table 1 ). + denotes a lead(pb) - free/rohs - compliant package. t&r and t = tape and reel. package information for the latest package outline information and land patterns (footprints), go to www.maxim - ic.com/packages . note that a ?+?, ?#?, or ? - ? in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless o f ro hs status. package type package code outline no. land pattern no. 8 so (150 mils) s8+4 21- 0041 90- 0096 8 max u8+1 21- 0036 90- 0092
DS1100 7 of 7 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no cir cuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408 - 737 - 7600 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products. revision history revision date description pages changed 3/11 removed the dip packag e from general description , pin assignment , and ordering information (no longer available) ; changed sop package type to max; updated the absolute maximum ratings section; added the customer support email address to the e lectrical c haracteristics note 4; added the ordering information and package information tables 1? 6
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